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1 ps8932c 07/31/08 features ? 6 differential channel, 1 to 2 demux that will support 5.0gbps pciexpress gen2 signals on one path, and dp 1.1 signals on the second path ? insertion loss for high speed channels @ 2.0 gbps: -2.0db ? low bit-to-bit skew , 7ps max (between '+' and '-' bits) ? latched mux select ? matched paths for all pcie signals ? low crosstalk for high speed channels: -35db@2.5 ghz ? low off isolation for high speed channels: -35db@2.5 ghz ? v dd operating range: 3.3v 10% ? esd tolerance: 8kv hbm on display port path output 4kv hbm on pci-express path output ? low channel-to-channel skew, 35ps max ? packaging (pb-free & green): ? 56 tqfn (zfe) description pericom semiconductor?s pi3pcie2612-b one to two mux/ demux is targeted for next generation systems that combine pci- express gen2 signals with display port signals. application routing dp and pciexpress gen1 or gen2 signals with low signal attenuation. block diagram pin diagram (top-side view) pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout truth table (sel control) function sel pci-express gen2 path is active (tx) l digital video port is active (dx) h truth table (latch control) le# internal mux select 0 respond to changes on sel 1 latched in_0+ in_0 in_1+ in_1 in_2+ in_2- in_3+ in_3- out+ out - x+ x- d0+ d0 - d1+ d1 - tx0+ tx0- tx1+ tx1 - d2+ d2- d3+ d3- tx2+ tx2- tx3+ tx3- le# - - logic control sel aux+ aux- hpd nc rx0+ rx0- rx1+ rx1- gnd in_0+ in_0- in_1+ in_1- vdd in_2+ in_2- in_3+ in_3- gnd sel le# out+ out- gnd vdd x+ x- gnd gnd d2+ d2- d3+ d3- tx0+ tx0- tx1+ tx1- tx2+ tx2- tx3+ tx3- gnd vdd aux+ aux- hpd nc gnd gnd vdd rx1- rx1+ rx0- rx0+ vdd gnd gnd vdd d0+ d0- d1+ d1- vdd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 08-0147
2 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout application example gmch dp/tmds/ pcie genii x4 hpd / peg rx peg aux / peg rx x12 tx x14 rx peg rx peg rx x2 x2 x16 peg connector dp path will support 2.7 gbps path will support gbps pcie 5 dp/pcie2.0 (1:2) mux pi3pcie2612-b dx hpd aux rx rx tx in pin description pin number pin name type description 33 aux+ o differential input from hdmi/dp connector. aux+ makes a dif- ferential pair with aux-. aux+ is passed through to the out+ pin when sel = 1. 32 aux- o differential input from hdmi/dp connector. aux- makes a dif- ferential pair with aux+. aux- is passed through to the out- pin when sel = 1. 54, 53 d0+, d0- o analog ?pass through? output#1 corresponding to in_0+ and in_0-, when sel = 1. 52, 51 d1+, d1- o analog ?pass through? output#1 corresponding to in_1+ and in_1-, when sel = 1. 47, 46 d2+, d2- o analog ?pass through? output#1 corresponding to in_2+ and in_2-, when sel = 1. 45, 44 d3+, d3- o analog ?pass through? output#1 corresponding to in_3+ and in_3-, when sel = 1. 08-0147
3 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout pin number pin name type description 1, 11, 16, 20, 21, 28, 29, 35, 48, 49, 56 gnd power - ground. 31 hpd i the hpd signal comes from the hdmi or dp connector. this is a low frequency, 0v to 5v (hdmi) or 3.6v (dp) input signal at the connector. the hpd input at the mux is 3.6v max, so hdmi hpd must be shifted down from 5v before it is passed to the mux. 4 in_0+ i differential input from gmch pcie outputs. in_0+ makes a differential pair with in_0-. 5 in_0- i differential input from gmch pcie outputs. in_0- makes a dif- ferential pair with in_0+. 7 in_1+ i differential input from gmch pcie outputs. in_1+ makes a differential pair with in_1-. 8 in_1- i differential input from gmch pcie outputs. in_1- makes a dif- ferential pair with in_1+. 9 in_2+ i differential input from gmch pcie outputs. in_2+ makes a differential pair with in_2-. 10 in_2- i differential input from gmch pcie outputs. in_2- makes a dif- ferential pair with in_2+. 12 in_3+ i differential input from gmch pcie outputs. in_3+ makes a differential pair with in_3-. 13 in_3- i differential input from gmch pcie outputs. in_3- makes a dif- ferential pair with in_3+. 3 le# i the latch gate is controlled by le. 3.6v tolerant, low-voltage, single-ended input. 30 nc do not connect 14 out+ o pass-through output from aux+ input when sel = 1. pass- through output from rx0+ input when sel = 0. 15 out- o pass-through output from aux- input when sel = 1. pass- through output from rx0- input when sel = 0. 26 rx0+ i/o differential input from pcie connector or device. rx0+ makes a differential pair with rx0-. rx0+ is passed through to the out+ pin when sel = 0. 25 rx0- i/o differential input from pcie connector or device. rx0- makes a differential pair with rx0+. rx0- is passed through to the out- pin when sel = 0. 24 rx1+ i differential input from pcie connector or device. rx1+ makes a differential pair with rx1-. rx1+ is passed through to the x+ pin when sel = 0. (continued) 08-0147
4 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout pin number pin name type description 23 rx1- i differential input from pcie connector or device. rx1- makes a differential pair with rx1+. rx1- is passed through to the x- pin on a path that matches the rx1+ to x+ path. 2 sel i sel controls the mux through a ow-through latch. 3.6v toller- ant low-voltage single-ended output sel = 0 for pcie mode sel = 1 for dp mode 43, 42 tx0+,tx0- o analog ?pass through? output#2 corresponding to in_0+ and in_0-, when sel = 0. 41, 40 tx1+, tx1- o analog ?pass through? output#2 corresponding to in_1+ and in_1-, when sel = 0. 39, 38 tx2+, tx2- o analog ?pass through? output#2 corresponding to in_2+ and in_2-, when sel = 0. 37, 36 tx3+, tx3- o analog ?pass through? output#2 corresponding to in_3+ and in_3-, when sel = 0. 6, 17, 22, 27, 34, 50, 55 vdd power 3.3v dc supply, 3.3v +/- 10% 18 x+ i/o hpd: low frequency, 0v to 5v/3.3v (nominal) input signal at the connector. this signal comes from the hdmi/dp connector. x+: analog ?pass through? output corresponding to rx1+. 19 x- i x- is an analog ?pass-through? output corresponding to the rx1- input. the path from rx1- to x- must be matched with the path from rx1+ to x+. x+ and x- form a differential pair when the pass-through mux mode is selected. 08-0147
5 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout recommended operating conditions symbol parameter conditions min typ max units vdd 3.3v power supply 3.0 3.3 3.6 v idd total current from vdd 3.3v supply 0 2.5 ma tcase case temperature range for operation within spec. -40 85 celcius electrical characteristics storage temperature ....................................................?65c to +150c supply voltage to ground potential ................................?0.5v to +4.6v dc input voltage .............................................................. ?0.5v to v dd dc output current ....................................................................... 120ma power dissipation ........................................................................... 0.5w note: stresses greater than those listed under max i mum rat ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. expo- sure to absolute max i mum rating con di tions for extended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) dc electrical characteristics (t a = ?40c to +85c, v dd = 3.3v 10%) parameter description test conditions min typ (1) max units v ih-en (2) input high level 2.0 3.6 v v il-en (2) input low level 0 0.8 v i in_en (2) input leakage current measured with input at v ih-en max and v il-en min ?10 10 ua r on on resistance v dd = min., v in = 1.3v, i in = 40ma 10 ohm c on on channel capacitance v in = 0, v dd = 3.3v 3.0 pf note: 1. typical values are at v dd = 3.3v, t a = 25c ambient and maximum loading. 2. for sel and le# inputs 08-0147
6 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout switching characteristics (t a = -40o to +85oc, v dd = 3.3v10%) parameter description test conditions min. typ. max. units t pzh , t pzl line enable time - sel to d x , t xy , r xy , aux, hpd see "test circuit for electri- cal characteristics" 0.5 12.0 ns t phz , t plz line disable time - sel to d x , t xy , r xy , aux, hpd see "test circuit for electri- cal characteristics" 0.5 12.0 ns t b-b bit-to-bit skew within the same differential pair see "test circuit for electri- cal characteristics" 7ps t ch-ch channel-to-channel skew see "test circuit for electri- cal characteristics" 35 ps dynamic electrical characteristics for in_x+/-, rxy+/-, and txy+/- parameter description test conditions min. typ. (1) max. units ddil differential insertion loss f=1.2ghz f=2.5ghz f=5.0ghz f=7.5ghz -1.5 -2.0 -5.0 -9.0 db ddil off differential off isolation f= 0 to 3.0ghz f= 5.0ghz -23.0 -20.0 ddrl differential return loss f= 0 to 2.8ghz f= 2.8 to 5.0ghz f= 5.0 to 7.5ghz -14.0 -8.0 -4.0 ddnext near end crosstalk f= 0 to 2.5ghz f= 2.5 to 5.0ghz f= 5.0 to 7.5ghz -32.0 -26.0 -20.0 dynamic electrical characteristics for dx+/- parameter description test conditions min. typ. (1) max. units ddil dp display port differential insertion loss f= 0 to 1.35ghz f= 1.35 to 2.7ghz -1.5 -4.5 db ddrl dp display port differential return loss f= 0 to 2.7ghz -14 ddnext- dp display port near end crosstalk f= 0 to 2.7ghz -32.0 08-0147
7 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout differential insertion loss differential return loss 08-0147
8 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout off isolation crosstalk 08-0147
9 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout tx eye diagram, 5.0 gbps dx eye diagram, 2.7 gbps 08-0147
10 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout test circuit test circuit test circuit 08-0147
11 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout switch positions test switch t plz , t pzl 2 x v dd t phz , t pzh gnd prop delay open switching waveforms voltage waveforms enable and disable times t plz v dd /2 v dd /2 v dd v oh 0v v ol v dd/2 v dd/2 t phz t pzl t pzh output 1 output 2 v ol v oh sel v ol + 0.15v v oh ? 0.15v r t 4pf c l v dd v in v out 200-ohm 200-ohm 2 x v dd pulse generator d.u.t test circuit for electrical characteristics (1-5) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = termination resistance: should be equal to z out of the pulse generator 3. output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50 , t r 2.5ns, t f 2.5ns. 5. the outputs are measured one at a time with one transition per measurement. 08-0147
12 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout applications information differential input characteristics for in_x+/- and rxx+/- signals. symbol parameter min nom max units comments tbit unit interval 199.94 200.00 200.06 ps de ned by gen2 spec. v rx-diffp-p differential input peak to peak voltage 0.175 1.200 v vrx-diffp-p = 2*|vrx- d+ - vrx-d-|. applies to in_d and rx_in signals. t rx-eye minimum eye width at in_d input pair. tbd tbit v cm-ac-pp ac peak common- mode input voltage 100 mv vcm-ac-pp = |vrx-d+ + vrx-d-| / 2 ? vrx-cm-dc. vrx-cm-dc = dc(avg) of |vrx-d++ vrx-d-| / 2 vcm-ac-pp includes all frequencies above 30khz. z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. z rx-dc dc input impedance 40 50 60 required in_d+ as well as in_d- dc impedance (50 +/- 20% tolerance). includes mux resistance. v rx-bias rx input termination voltage 0 2.0 v intended to limit power- up stress on pcie output buffers. ddil differential insertion loss -[0.6*(f)+0.5] db up to 2.5 ghz (for example, -2 db at f = 2.5 ghz); -[1.2*(f-2.5)+2] db for 2.5 ghz < f 5 ghz (for exam- ple, -5 db at f = 5 ghz); -[1.6*(f-5)+5] db for 5 ghz < f 7.5 ghz (for example, -9 db at f = 7.5 ghz); db ddrl differential return loss -14 db up to 2.8 ghz; -8 db up to 5 ghz; -4 db up to 7.5 ghz. db ddnext near end crosstalk -32 db max up to 2.5 ghz; - 26 db max up to 5.0 ghz; -20 db max up to 7.5 ghz; db ddil when switch is off differential insertion loss when switch is off -20 db up to 3 ghz; db 08-0147
13 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout pcie gen2 output characteristics symbol parameter min nom max units comments z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. z rx-dc dc input impedance 40 50 60 required in_d+ as well as in_d- dc imped- ance (50 +/- 20% tol- erance). includes mux resistance. v rx-bias rx input termination volt- age 0 2.0 v intended to limit pow- er-up stress on pcie output buffers. ddil differential insertion loss -[0.6*(f)+0.5] db up to 2.5 ghz (for example, -2 db at f = 2.5 ghz); -[1.2*(f-2.5)+2] db for 2.5 ghz < f 5 ghz (for exam- ple, -5 db at f = 5 ghz); -[1.6*(f-5)+5] db for 5 ghz < f 7.5 ghz (for example, -9 db at f = 7.5 ghz); db ddrl differential return loss -14 db up to 2.8 ghz; -8 db up to 5 ghz; -4 db up to 7.5 ghz. db ddnext near end crosstalk -32 db max up to 2.5 ghz; -26 db max up to 5.0 ghz; -20 db max up to 7.5 ghz; db ddil when switch is off differential insertion loss when switch is off -20 db up to 3 ghz; db 08-0147
14 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout display port output characteristics symbol parameter min nom max units comments tbit unit interval 333 ps normal tbit at 2.7gb/ s=370ps. 333ps=370ps- 10% v rx-diffp-p differential input peak to peak voltage 0.340 1.38 v vrx-diffp-p = 2*|vrx-d+ - vrx-d- |. applies to in_d and rx_in signals. t jit jitter added to high-speed signals 7.4 ps jitter budget for high- speed signals as they pass through the display mux. 7.4ps = 0.02 tbit at 2.7gb/s ddil differential insertion loss -[0.75*(f)+0.5] db up to 1.35 ghz; -[2.2*(f-1.35)+1.5] db for 1.35 ghz < f 2.7 ghz db for example, -1.5 db at f = 1.35 ghz for example, -4.5 db at f = 2.7 ghz ddrl differential return loss -14 db up to 2.7 ghz db ddnext near end crosstalk -32 db max up to 2.7 ghz db hpd input characteristics symbol parameter min nom max units comments v ih-hpd input high level 3.6 v low-speed input chang- es state on cable plug/ unplug. v il-hpd hpd input low level 0 v i in_hpd hpd input leakage cur- rent |10| ua measured with hpd at vih-hpd max and vil-hpd min t hpd hpd_in to hpd propa- gation delay. 200 ns time from hpd_in changing state to hpd changing state. includes hpd rise/fall time. t rf-hpd hpd rise/fall time. 120 ns time required to transi- tion from voh-hpd to vol-hpd or from vol-hpd to voh- hpd. termination resistors symbol parameter min nom max units comments r ddc ddc termination resis- tors 1.3k 1.5k 2.2k w applies to both 3.3v and 5v pull up resistors. 08-0147
15 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout signal integrity requirements and test procedures for 5.0 gb/s parameter procedure requirements differential insertion loss (ddil) eia 364-101 the eia standard shall be used with the following considerations: 1. the measured differential s parameter shall be referenced to a 100 ohms differential impedance. 2. the test xture shall meet the test xture requirement de ned in section 1.12. 3. the test xture effect shall be removed from the measured s parameters. refer to note 1. -[0.6*(f)+0.5] db up to 2.5 ghz (for example, -2 db at f = 2.5 ghz); -[1.2*(f-2.5)+2] db for 2.5 ghz < f 5 ghz (for example, -5 db at f = 5 ghz); -[1.6*(f-5)+5] db for 5 ghz < f 7.5 ghz (for example, -9 db at f = 7.5 ghz); refer to figure 1. differential return loss (ddrl) eia 364-108 the eia standard shall be used with the following considerations: 1. the measured differential s parameter shall be referenced to a 100 ohms differential impedance. 2. the test xture shall meet the test xture requirement in section 1.12. 3. the test xture effect shall be removed. refer to note 1. -14 db up to 2.8 ghz; -8 db up to 5 ghz; -4 db up to 7.5 ghz. refer to figure 2. intra-pair skew intra-pair skew must be achieved by design; measurement not required. 5 ps max differential near end crosstalk (ddnext) eia 364-90 the eia standard must be used with the following considerations: 1. the crosstalk requirement is with respect to all the adjacent dif- ferential pairs -32 db max up to 2.5 ghz; -26 db max up to 5.0 ghz; -20 db max up to 7.5 ghz; see figure 3. differential insertion loss (ddil) when switch is turned off eia 364-101 -20 db up to 3 ghz; notes: 1. the speci ed s parameters requirements are for switch component only, not including the test xture effect. while the trl calibration method is recommended, other calibration methods are allowed. switch signal integrity requirements and test procedures for 5.0 gb/s signal integrity requirements for 5.0 gb/s applications of the switch are speci ed. also included are the requirements of the test xture for switch s-parameter measurements. signal integrity requirements the procedures outlined in ansi electronics industry alliance (eia) standards documents shall be followed: ? eia 364-101 ? attenuation test procedure for electrical connectors, sockets, cable assemblies or interconnection systems ? eia 364-90 ? crosstalk ratio test procedure for electrical connectors, sockets, cable assemblies or interconnection systems ? eia 364-108- impedance, re ection coef cient, return loss, and vswr measured in the time and frequency do- main test procedure for electrical connectors, sockets, cable assemblies or interconnection systems 08-0147
16 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout 0 1 2 3 4 5 6 7 8 9 10 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 frequency, ghz differential insertion loss [db] sdd21 zref=100 ohms figure 1: illustration of differential insertion loss requirement. 0 1 2 3 4 5 6 7 8 9 10 -30 -25 -20 -15 -10 -5 0 frequency, ghz differential return loss [db] sdd11 zref=100 ohms figure 2: illustration of differential return loss requirement. 08-0147
17 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout 0 1 2 3 4 -10 5 6 78 -45 -40 -35 -30 -25 -20 sdd21 zref=85 ohms -15 frequency, ghz differential near end crosstalk, db figure 3: illustration of different ial near end crosstalk requirement. switch test fixture requirements the test t xture for switch s-parameter measurement shall be designed and built to speci t c requirements, as described below, to ensure good measurement quality and consistency: ? the test t xture shall be a fr4-based pcb of the microstrip structure; the dielectric thickness or stackup shall be about 4 mils. ? the total thickness of the test t xture pcb shall be 1.57 mm (0.62?). ? the measurement signals shall be launched into the switch from the top of the test t xture, capturing the through-hole stub effect. ? traces between the dut and measurement ports (sma or microprobe) should be uncoupled from each other, as much as possible. therefore, the traces should be routed in such a way that traces will diverge from each other exiting from the switch pin t eld. ? the trace lengths between the dut and measurement port shall be minimized. the maximum trace length shall not exceed 1000 mils. the trace lengths between the dut and measurement port shall be equal. ? all of the traces on the test board and add-in card must be held to a characteristic impedance of 50 ohms with a tolerance of +/- 7%. ? sma connector is recommended for ease of use. the sma launch structure shall be designed to minimize the connection discontinuity from sma to the trace. the impedance range of the sma seen from a tdr with a 60 ps rise time should be within 50+/-7 ohms. 08-0147
18 ps8932c 07/31/08 pi3pcie2612-b high bandwidth, 6-differential channel 1:2 dp/pcie gen2 display mux, btx pinout ordering information ordering code package code package description pi3pcie2612-bzfe zf pb-free & green, 56-contact tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging packaging mechanical: 56-contact tqfn (zfe) description: 56-contact, thin fine pitch quad flat no-lead (tqfn) package code: zf56 document control #: pd-2024 revision: c date: 05/15/08 pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 08-0147

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